1. Field of the Invention
This invention relates to a structure of a capacitor in a semiconductor device, and more particularly to a structure of a capacitor in a dynamic random access memory (DRAM) device.
2. Description of Related Art
For memory devices with high integration such as DRAM devices with memory capacity of 256 Megabit, their capacitor need a dielectric thin film to be constructed as the three dimensional structures like stacked type or trench type. Thus these memory devices should have a large area of the dielectric thin film to store the charge to avoid the soft error. Utilizing a method of the low pressure chemical vapor deposition (LPCVD), which is one of applications of the chemical vapor deposition (CVD), to make the dielectric thin film made of Ta.sub.2 O.sub.5 is popular for the present because this material produces a dielectric constant about 25, which is far larger than that of oxide, and has a better ability of step coverage. The step coverage means that the covering surface is kept in a step shape without being rounded.
In the design of a very large scale integration circuit (VLSI), to increase the capacitance in the integrated circuits (ICs), it has three effective methods. The first is that the thickness of the dielectric thin film mediated between two electrodes is reduced because the capacitance is inversely proportional to the distance between these two electrodes. This method can increase the capacitance effectively but is difficult to be controlled to obtain a uniform and stable dielectric thin film. The second method is that the interfacial area between the dielectric thin film and the electrode is increased because the capacitance is proportional to the size of this area. For the present, to increase the size of the interfacial area, such as a fin type or a hemispheric grain type is applied but has a difficulty for massive production due to the complexity of fabrication. Another option is taking a cylindrical type. The third method is that the dielectric constant is increased such as the materials of Ta.sub.2 O.sub.5, Lead Zirconium Titanate (PZT) composed of Pb(Zr,Ti)O.sub.3, and Bismuth Strontium Titanate (BST) composed of (Ba,Sr)TiO.sub.3, which have high dielectric constant.
In the conventional method of fabricating a semiconductor device, a polysilicon material is usually to be taken for the electrodes of the capacitors. In this case, the higher the temperature is used in the process of annealing on the dielectric thin film, the lesser the defect exists in the dielectric thin film. This means the quality of the dielectric thin film should be better. But, if the temperatures used in the process of annealing is too high, an native oxide is easily produced around the interface between the dielectric thin film and the lower electrode to reduce the capacitance. Here, it doesn't happen around an interface between the dielectric thin film and an upper electrode because the upper interface has not been formed yet. On the contrary, if the temperatures used in the process of annealing is too low, and then the defect existing in the dielectric thin film could not effectively be removed.
Therefore, so far, to prevent the bad situations as described above, a metal layer, generally, is taken instead for the electrodes, which is usually made of a polysilicon layer in the old method. That is to say a metal insulator metal (MIM) capacitor, which is especially applied in a nonvolatile ferroelectric memory (FeRAM) and a DRAM with high integration.
The metal layer of the MIM capacitor is usually made of conductive materials such as Platinum, Iridium, Iridium oxide or Ruthenium oxide. Unfortunately, the conventional MIM capacitor usually has a thick lower electrode, on which the etching is complicate and taking time. Except this, it has another problem that because the profile of the pitted contact window is usually steeper, it causes not only the difficulty of the alignment of a source/drain region but also the bad quality of the ability of the step coverage. It is therefore that the filling of a layer of polysilicon and an glue/barrier layer into the pitted contact window should be done before the material for the lower electrode is filled in. This causes the complexity of the fabrication.
FIG. 1A through FIG. 1H illustrate the sectional plots of a capacitor of a DRAM in the conventional fabricating procedure. The like marks represent the like elements in the FIGs.
Referring to FIG. 1A, two gates 102 with an identical structure but only one being marked are shown in the figure over a substrate 100 on a substrate surface 101. The FIG. 1A further includes a source/drain region 110 and a commonly used source/drain region 110a between the gates 102 under the substrate surface 101. One of gates 102 with marks has a doped polysilicon layer 106 covered by a spacer 104 and a cap layer 108. The source/drain region 110 and the commonly used source/drain region 110a are the doped area with a structure of lightly doped drain (LDD) and can be formed by doing the ion implantation, in which the structure of the gates 102 is treated as the mask. The lightly doped areas, located on the fringe of the source/drain region 110 and the commonly used source/drain region 110a with shallower depth, are formed first before the spacer 104 is formed. A slightly heavier doped areas with deeper depth are formed on the central part of the source/drain region 110 and the commonly used source/drain region 110a after the spacer 104 is formed. The spacer 104 typically is made of silicon oxide or silicon nitride. After the source/drain region 110 and the commonly used source/drain region 110a are fully formed, an insulating layer 112 is formed over the substrate 100 and the gates 102.
Referring FIG. 1A and FIG. 1B, by utilizing the etching technology, a contact window 111 is defined on the insulating layer 112 to become an insulating layer 112a. The contact window 111 exposes part of the commonly used source/drain region 110a.
Referring FIG. 1B and FIG. 1C, a polysilicon layer 114 preferably made of doped polysilicon by the method of LPCVD is formed over the insulating layer 112a with the contact window 111 being filled.
Referring FIG. 1C and FIG. 1D, by utilizing a process of etch back, the polysilicon layer 114 is etched gradually until the insulating layer 112a has been exposed partly. After this procedure the polysilicon layer 114 becomes a polysilicon layer 114a.
Referring FIG. 1D and FIG. 1E, an glue/barrier layer 116 preferably made of Ti/TiAlN, respectively, is formed over the polysilicon layer 114a. Then the process of annealing is operated immediately. This process creates a TiSi.sub.2 layer 117 around the interface between the polysilicon layer 114a and the glue/barrier layer 116. This process also can enhance the ohmic contact between the polysilicon layer 114a and a lower electrode to reduce the resistance. The lower electrode is to be seen in the next FIGs.
Referring FIG. 1E and FIG. 1F, a conductive layer 118 is formed over the glue/barrier layer 116. The conductive layer acts as the lower electrode and is preferably made of one such as Pt, Iridium, Iridium oxide, or Ruthenium oxide by the preferred methods of CVD or sputtering.
Referring FIG. 1F and FIG. 1G, the lower electrode composed of a conductive layer 118a and an glue/barrier layer 116a as mentioned above is defined on both the conductive layer 118 and glue/barrier layer 116 by the photolithography etching technology.
Referring FIG. 1G and FIG. 1H, over a surface 120a, a dielectric thin film 120 is formed with a thickness about between 10 and 60 Angstrom. The dielectric thin film 120 is preferably made of one having high dielectric constant such as Ta.sub.2 O.sub.5, PZT or BST.
Then, a conductive layer 128 is formed over the dielectric thin film 120 to be an upper electrode and preferably is made of one such as Pt, Iridium, Iridium oxide or Ruthenium oxide and by the preferred methods of CVD or sputtering as done for the lower electrode.
The conventional structure of the MIM capacitor in the DRAM as described above has a number of drawbacks as follows:
1. If the thickness of the lower electrode is too thick for being able to hold more charges, the etching can not easily be done and cracks can easily happen around the interface between the lower electrode and the dielectric thin film to cause the leakage current.
2. The wall of the pitted contact window, almost vertical to the substrate surface, causes the difficulty of the alignment on the glue/barrier layer. Further, because the ability of step coverage for the metal material is poor, before the lower electrode is made, the polysilicon layer and the glue/barrier layer should be filled in the pitted contact window. This increases the complexity of the fabricating procedure.
3. The conventional MIM capacitors are formed on the insulating layer so that the IC with high integration can not be effectively improved due to the distance between the capacitors can not be effectively reduced. This is because a micro-loading, which is a micro-conducting-path, can easily happen between the conventional MIM capacitors if the capacitors are too close.